(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes related to formation of insulative layers for integrated circuits.
(2) Background of the Invention and Description of Previous Art
Integrated circuits(ICs) are manufactured by first forming discrete semiconductor devices within the surface of silicon wafers. A multi-level metallurgical interconnection network is then formed over the devices contacting their active elements and wiring them together to create the desired circuits. A conventional method for forming an interconnection wiring level begins by first depositing an insulating layer over the discrete devices, patterning and etching openings into this layer. A conductive layer is next applied over the insulating layer, patterned, and etched to form wiring interconnections between the device contacts thereby creating a first level of basic circuitry. In some applications conductive plugs are first formed in the openings prior to the deposition of the conductive layer. These basic circuits are then further interconnected by utilizing additional wiring levels laid out over additional insulating layers with conductive pass throughs. The conductive pass-throughs which access the active areas of the semiconductive devices through openings in the lowermost insulative layer are referred to as contacts while those pass-throughs which interconnect metallization levels are referred to as vias.
The insulative layers which separate the interconnection wiring layers are called upon to provide, in addition to electrical insulation of conductive components, good step coverage over the subjacent wiring pattern as well as a reasonably planar surface upon which to form the superjacent wiring pattern. In order to achieve these requirements, composite insulative layers are often used. A first insulative layer which can be applied with good edge coverage is applied over the wiring pattern. A second insulative layer, which can be directed towards surface planarization is then applied over the first.
Murao, U.S. Pat. No. 5,518,962 cites a relatively thin layer of BPSG (borophosphosilicate glass) deposited over a metallization pattern by a CVD (chemical vapor deposition) process. A layer of TEOS (tetraethoxysilane) silicon oxide deposited over the BPSG by an APCVD (atmospheric pressure chemical vapor deposition) process provides good step coverage. The TEOS silicon oxide layer is planarized by using a sacrificial SOG (spin-on glass) etchback planarization process. A second layer of APCVD TEOS silicon oxide then applied to complete the interlayer insulating film.
Huang, et. al., U.S. Pat. No. 5,736,450 cites the use of a dual layer dielectric film wherein a TEOS silicon oxide layer is deposited by SACVD (sub atmospheric chemical vapor deposition) over a BPSG layer deposited by PECVD (Plasma enhanced chemical vapor deposition). The fast etching TEOS oxide provides a favorable etch rate differential with respect to the BPSG. This permits the elimination of an etch stop layer in the application.
Suzuki, U.S. Pat. No. 5,332,694 cites a layer of PECVD silicon oxide deposited on an aluminum metal pattern. Like Murao, a second insulative layer of APCVD TEOS silicon oxide is deposited over the PECVD silicon oxide. A spin-on organosilicon coating is then used for etchback planarization. The APCVD silicon oxide has a good planarization etch rate compared to that of the spin-on coating, and no residual spin-on coating is left behind after the etchback planarization. This eliminated a problem of de-lamination of the APCVD silicon oxide from residual spin-on coating. Suzuki, et. al., U.S. Pat. No. 5,607,880 first deposits a first silicon oxide layer over an aluminum pattern by PECVD and then subjects the surface of this layer to dry etching in a plasma containing a fluorine compound. This surface treatment eliminates bubbles and voids in a second silicon oxide layer which is subsequently deposited by APCVD using TEOS and O.sub.3 (ozone).
Sukharev, U.S. Pat. No. 5,710,079 cites an APCVD process for the deposition of silicon oxide from TEOS in the presence of ozone, water, and hydrogen peroxide wherein ultraviolet radiation is employed to enhance the decomposition of ozone molecules. The atomic oxygen thereby produced reacts with water molecules to produce hydroxyl radicals which, in turn, enhance the decomposition of TEOS. The deposition rate of the film is increased and the occurrence of bubbles and voids in the film is reduced.
In the current application, a BPTEOS (BPSG deposited from TEOS and doped with boron and phosphorous) layer is deposited onto a PECVD silicon oxide layer by an APCVD process using ozone. BPSG is used extensively as an interlevel dielectric since it combines protection against instability due to ionic contamination and can be reflowed at low temperatures to improve surface planarity.
Unlike APCVD TEOS silicon oxide films, APCVD BPSG films do not exhibit surface roughness or bubble occlusion. However, the APCVD BPSG films are less dense than corresponding BPSG films formed by LPCVD or PECVD. Generally films deposited by APCVD or SACVD are of lower density than corresponding films deposited by other CVD methods. As a result, the APCVD BPSG films shrink considerably during a subsequent reflow process step. APCVD silicon oxide films do not experience such shrinkage and do not flow to any appreciable extent during subsequent annealing. It has been found by the present investigators that in regions where a composite PECVD silicon oxide/APCVD BPSG IMD (inter metal dielectric) layer dips into narrow, high aspect ratio, pockets, such as between closely spaced polysilicon gate lines in memory circuits, there is a tendency for the APCVD BPSG layer to detach from the subjacent oxide layer. This delamination is a direct result of the high stresses induced in these narrow regions by the shrinkage of the BPSG layer during annealing.
FIG. 1A and FIG. 1B show an example to illustrate the formation of voids in high aspect ratio pockets. Referring first to FIG. 1A, a wafer silicon 10 with two parallel conductive lines 14 is shown in cross section, the conductive lines 14 running perpendicular to the plane of the page. The conductive lines 14 are shown patterned over a silicon oxide layer 12. In order to form an interlevel dielectric layer over the conductive lines 14, a silicon oxide layer 18 is first conformally deposited over the line 14 by a CVD process. Next a thicker layer of BPSG 20 is deposited over the silicon oxide layer 18. The method of choice for depositing the BPSG layer 20 is APCVD which tends to form films of lower density than other CVD methods.
Referring now to FIG. 1B, the surface of the BPSG layer 20 is planarized by thermally reflowing at a temperature of about 900.degree. C. At this temperature the BPSG is sufficiently fluid to flow towards a planar surface. The dashed line 21 in the figure denotes the original surface (FIG. 1A) shown before thermal reflow treatment. However, it has been observed by the current investigators, that if the density of the as-deposited BPSG 20 is too low, the greater amount of shrinkage of the BPSG layer within the high aspect ratio pocket 16 is too great to be compensated by fluid flow. As a result, the BPSG detaches from the underlying silicon oxide during the reflow step and a void 22 is formed in the base of the pocket 16. Once detachment occurs, surface tension of the BPSG over the void 16 sustains and enhances the detachment.
The probability of void formation depends upon the aspect ratio of the pocket 16 and the magnitude of the respective depth or width of the pocket. The presence of voids is undesirable and usually leads to yield losses due to shorts, leakages, and overall performance degradation. Detachment of thick APCVD silicon oxide films from subjacent thinner films is not observed by either Suzuki or Murao because, although subjected to high annealing temperature, the APCVD silicon oxide films do not flow as the BPSG films and therefore do not shrink to the extent that the BPSG film 20 does.
It would therefore be desirable to have an improved method for forming a BPSG layer over a PECVD silicon oxide layer by APCVD which would reduce the amount of thermal shrinkage of the BPSG during reflow and thereby prevent detachment of the BPSG layer in regions of high aspect ratio depressions in the subjacent silicon oxide layer. The method of this invention provides such a solution.